The present invention relates generally to a new semiconductor process and structure, and more particularly, to a new semiconductor process and structure which provides an edge seal with improved resistance to crack propagation and impurity ingress in semiconductor devices (also referred to herein as integrated circuit devices) with preferably high conductivity copper metallurgy and low-k dielectric material.
Semiconductor device interconnection technology has made giant advancements to meet the requirements of increased device density and circuit performance. To meet the ever increasing device density demand, a double damascene method for interconnecting the semiconductor devices is widely utilized. Among other attributes of double damascene methodology, it allows the definition of a pattern of interconnection lines and via-studs with essentially no restriction on materials used or number of layers of materials used in the interconnection. This feature of damascene methodology allowed the introduction of copper metallurgy which requires a variety of barrier layers and different metal deposition methods. In order to meet the improved circuit performance by reducing the parasitic impedance losses, it was soon found that a low dielectric constant (xe2x80x9clow-kxe2x80x9d) dielectric material is essential to complement the increased conductivity offered by copper metallurgy. Accordingly, low-k dielectric material and copper metallurgy interconnection defined by dual damascene methodology is the present day choice for interconnections in high performance semiconductor device processing.
One of the main drawback of this scheme is the high corrosion and oxidation susceptibility of copper metal. To protect copper features from corrosion, a variety of barrier metals, for example tantalum/tantalum nitride, are used as sheathing for copper interconnection lines and via-studs. However, these barrier layers reduce the cross section of the high conductivity interconnection lines and via-studs and hence must be made as thin as possible. For feature widths in the tenth of a micron regime, the film thickness allowed for each barrier layer is about 80 Axc2x0, which is barely one or two grains thick. This thickness, however, is adequate to prevent copper corrosion and oxidation by impurities in the surrounding dielectric provided the ingress of impurities through the chip edge is prevented.
An edge seal around the periphery of a semiconductor device has been proposed by others to act as a firewall to prevent ingress of oxygen, moisture or any impurity from chip edges. One embodiment of a present art edge seal, partly shown in FIG. 1, comprises stacked via-studs (CA, V1, . . . ) and copper interconnection lines (M1, M2, . . . ) surrounded by inter-level dielectric (D1, D2, . . . ) and composite dielectric layers of BLOK hard mask (HM1,HM2, . . . ) and silicon-nitride cap (SN1,SN2, . . . ). BLOK (trademark of Applied Materials Inc.) is a plasma enhanced chemical vapor deposition (PECVD) deposited silicon carbide film. The coupled contact array (CA) via-studs and M1 interconnection lines, or V1 via-studs and M2 interconnection lines, are comprised of copper metallurgy and defined simultaneously by a double damascene method as is well known to those skilled in the art. The composite dielectric layers HM1/SN1, HM2/SN2, etc. are necessary layers in a double damascene method for improved process yield and reliability of interconnections.
The damascene process will be briefly described. Following the formation of tungsten or silicon local interconnects M0, a first inter level dielectric layer D1 and BLOK hard mask layer HM1 is deposited. Usually, a via-stud pattern CA is first photolithographically defined in HM1 and the HM1 is etched followed by a partial etch of D1. A pattern for next level of interconnection line M1 is then photolithographically defined in HM1, the HM1 etched and the D1 is etched until the underneath metal M0 is exposed. This is followed by deposition of TaN/Ta barrier layers, a copper seed layer and electroplated copper. The wafer is then chemically mechanically (hereafter chem-mech) polished by conventional methods to remove excess metals atop HM1. The BLOK hard mask layer (HM1) is essential for stopping the chem-mech polishing operation on a planar surface. A silicon nitride layer (SN1) is then deposited to improve the adhesion of the next level of materials. This SN1 layer gets etched out underneath the via-studs V1 during the operation to form the next level of via-stud/interconnection lines. The process is repeated as many times as the number of interconnection levels required.
Whereas the present day edge seal with silicon dioxide interlevel dielectric is generally satisfactory, the present day edge seal scheme is inadequate for corrosion protection when a low-k dielectric, usually a porous material with high permeability for moisture and oxygen, e.g. SiLK, is used for the interlevel dielectric. SiLK (a trade mark of Dow Chemical Co., Midland, Mich.) is a fluorinated organic polymer and when spun on a semiconductor wafer and cured at about 400xc2x0 C., forms a low-k dielectric film. During the wafer dicing operation, cracks are easily initiated from the chipping of the edge of the diced semiconductor device (shown in FIG. 1). The crack initiation is more pronounced at the interface of the SiLK and the nitride cap as shown in FIG. 2. The weak adhesion between SiLK and the nitride cap provides an easy path for propagation of cracks generated by the wafer dicing operation, thereby exposing the edge seal metallurgy to the ambient, which leads to corrosion of the edge seal. The volume expansion of the corroded edge seal metallurgy generates yet another series of cracks leading towards the interconnections, which in turn corrode and cause device failure.
Accordingly, methods must be sought to reduce crack generation and crack propagation propensity.
Tsai et al. U.S. Pat. No. 6,133,144, the disclosure of which is incorporated by reference herein, discloses a double damascene method in a silicon dioxide dielectric having copper wiring to reduce the parasitic capacitance by reducing the effective inter level dielectric thickness, without removal of any etch barrier layer, by a judicial design and masking scheme.
Lin U.S. Pat. No. 6,140,220, the disclosure of which is incorporated by reference herein, discloses incorporating a silicon nitride sleeve around a copper via-stud with an objective to increase the conductive cross-section of via-stud. The dielectric layer is silicon dioxide. Whereas this silicon nitride sleeve may provide an added barrier for via-studs, it fails to protect the whole edge-seal structure because the sidewalls of the conductor lines do not have this added barrier of silicon nitride.
Chen U.S. Pat. No. 6,200,890, the disclosure of which is incorporated by reference herein, discloses providing an oxide layer over the top surface and top half of the sidewalls of copper conductor lines with an objective to improve electromigration life in copper metallurgy and to reduce intra-level leakage. Accordingly, application of Chen""s scheme will not meet the objective to cover the sidewalls of the edge seal, which is comprised of interconnection lines as well as via-studs. Moreover, while Chen mentions the use of a low-k material, his teachings are not directly applicable if the low-k dielectric is SiLK, since Chen does not address the extremely high polishing rate of SiLK.
Jang et al. U.S. Pat. No. 6,268,294, the disclosure of which is incorporated by reference herein, discloses a method to chemically passivate the etched sidewalls of dielectric prior to filling the damascene cavity with metals. This reacted layer provides an added barrier layer but it fails to protect the whole edge-seal structure because the sidewalls of the conductor lines do not have this added barrier. Further, this method is specifically directed to polymeric dielectrics and is not applicable to chemically inert dielectric material like SiLK.
Lao U.S. Pat. No. 6,287,960, the disclosure of which is incorporated by reference herein, discloses the problem of how to center the stud part of a dual damascene structure relative to the trench part wherein an oxide dielectric and copper wiring are utilized.
Chow et al. IBM Research Disclosure Number 316 (August 1990), the disclosure of which is incorporated by reference herein, discloses a method to provide a silicon oxide or silicon nitride sidewall spacer around tungsten via-studs in a polyimide dielectric to avoid interaction of the tungsten with moisture evolving from the polyimide. The disclosed method, however, fails to protect the whole edge seal structure because the sidewalls of the conductor lines do not have this added barrier.
Bearing in mind the problems and deficiencies of the prior art, it is therefore a purpose of the present invention to provide a semiconductor device having copper interconnections and low-k dielectric with an edge seal which is resistant to ingress of impurities and thereby more resistant to corrosion.
Another purpose of the present invention is to provide an edge seal which is more resistant to initiation and propagation of dicing induced cracks.
It is another purpose of the present invention to provide a wall of dense dielectric material along side the metal edge seal wall.
It is yet another purpose of the present invention to provide a fabrication method of a semiconductor device having a composite dielectric comprising a low-k dielectric material and a hard mask layer whereby the hard mask layer of the composite dielectric does not extend up to the metallurgy of the edge seal.
The purposes of the invention have been achieved by providing, according to a first aspect of the present invention, a method of forming an edge seal along a periphery of an integrated circuit device to provide increased corrosion and oxidation resistance to metallization of the integrated circuit device, the method comprising the steps of:
a. providing a semiconductor substrate having a metallic feature therein;
b. depositing a layer of dielectric material over the semiconductor substrate and metallic feature, the layer of dielectric material comprising a low-k dielectric material;
c. selectively removing a portion of the layer of dielectric material to form a cavity and expose a portion of the metallic feature;
d. conformally depositing a layer of an insulation material in the cavity and over the layer of dielectric material, wherein the insulation material and dielectric material are different materials;
e. removing horizontal portions of the layer of insulation material so as to expose at least the metallic feature in the cavity;
f. depositing a barrier metal on the layer of insulation material in the cavity and on the exposed metallic feature;
g. depositing a high conductivity metal in the cavity to fill the cavity; and
h. planarizing the semiconductor substrate down to the layer of dielectric material.
According to a second aspect of the present invention, there is provided an edge seal around the periphery of an integrated circuit device comprising:
a. a semiconductor substrate;
b. a layer of dielectric material over the semiconductor substrate, the layer of dielectric material comprising a low-k dielectric material;
c. a metallic wall of a high conductivity metal in the layer of dielectric material; and
d. a layer of insulation material between the metallic wall and the dielectric material, wherein the insulation material and dielectric material are different materials.
According to a third aspect of the present invention, there is provided a method of forming an edge seal along a periphery of an integrated circuit device to provide increased corrosion and oxidation resistance to metallization of the integrated circuit device, the method comprising the steps of:
a. providing a semiconductor substrate having a metallic feature therein;
b. depositing a layer of dielectric material over the semiconductor substrate and metallic feature, the layer of dielectric material comprising a low-k dielectric material;
c. selectively removing a portion of the layer of dielectric material to form two first cavities and expose a portion of the metallic feature;
d. depositing an insulation material to fill the two first cavities, wherein the insulation material and dielectric material are different materials;
e. selectively removing a portion of the layer of dielectric material, and any overlying insulation material to form a second cavity;
f. depositing a barrier metal in the second cavity and on the exposed metallic feature;
g. depositing a high conductivity metal in the second cavity to fill the cavity; and
h. planarizing the semiconductor substrate down to the layer of dielectric material.
According to a fourth aspect of the present invention, there is provided an edge seal around the periphery of an integrated circuit device comprising:
a. a semiconductor substrate;
b. a layer of dielectric material over the semiconductor substrate, the layer of dielectric material comprising a low-k dielectric material;
c. a metallic wall in the layer of dielectric material; and
d. a wall of insulation material between the metallic wall and the periphery of the integrated circuit device wherein the insulation material and dielectric material are different materials.